![]() ![]() The reset signal will remain asserted for a minimum of 1ms (typically 1.4ms) after the supply voltage rises above this threshold, and/or the processor deasserts its reset signal. This device will assert the reset signal to the CY7C68001 (active Low) if its 3.3V supply voltage dips below 2.3V, or if it receives an external reset signal from the processor in the FPGA design. Reset of the USB interface device is provided through use of a supervisory reset circuit device – a MAX6315US26D1, from Maxim. Internal clocking for the USB transceiver (and various internal logic) is supplied from an internal PLL, which itself is driven by an external 24MHz crystal connected across the device's XTALIN and XTALOUT pins. Powered by the PB03's 3.3V supply, it supports Full (12Mbps) or High (480Mbps) speed operation.Īlthough the device is configured to provide a 16-bit bidirectional data bus, only the low-order byte ( USB_D) is used for communications with the processor. This device has a built-in USB transceiver and a Serial Interface Engine (SIE), which automatically manages the USB protocol. Providing the high-speed interface between a processor in an FPGA design and the USB bus is an EZ-USB SX2™ device (CY7C68001-56LFC, from Cypress Semiconductor). The port is provided courtesy of a USB B-type connector. The PB03 provides a USB 2.0 port, identical to that found on the NB2DSK01 motherboard. ![]()
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